Innovations technological

Position1:

Title: Functional Verification engineer (Pre-Silicon)

Location: Allentown, PA and Hillsboro, OR

Duration - 6+ months

# of Openings: 10

 

ONLY US Citizen/GCs Required!

1. Role: Pre-Silicon functional verification Senior Engineer:
2. Qualification: MS-EE
3. Experience Level:  4+ Years
4. Skill set and experience
1. At least  3+  years' experience in pre-silicon verification
2. Expertise in Building scalable HVL based verification environment from Scratch using System Verilog OVM/UVM
3. Good experience in System Verilog – OVM/UVM based verification environment development
4. Sound understanding of Random and constrained random-verification concepts
5. Experience with assertion based verification would be a plus
6. Understanding  PCI-E, USB, SATA, DDR3  type protocols would be a plus
5. Role included:
1. Driving the verification environment architecture
2. Creating test scenarios(System Verilog OVM)
3. Work with RTL teams to debug verification failures
4. Review and ensure that expected Code and functional coverage metrics are achieved

Position2:

Title: Functional Verification Lead (Pre-Silicon)

Location: Allentown, PA and Hillsboro, OR

Duration: 6+ months

# of Openings: 1

 

ONLY US Citizen/GCs Required!

 

1. Role: Pre-Silicon functional verification Lead/Senior Engineer:
2. Qualification: MS-EE
3. Experience Level:  8+ Years
4. Skill set and experience
1. At least  6+  years' experience in pre-silicon verification
2. 2+ Years of RTL Coding(Preferable)
3. Expertise in Building scalable HVL based verification environment from Scratch using System Verilog
4. Good experience in System Verilog – OVM/UVM based verification environment development
5. Sound understanding of Random and constrained random-verification concepts
6. Experience with assertion based verification would be a plus
7. Understanding  PCI-E, USB, SATA, DDR3, MIPI  type protocols would be a plus
8.  Ability to Guide 4-5 team members
5. Role includes:
1. Driving the verification environment architecture
2. Creating test scenarios(System Verilog OVM)
3. Work with RTL teams to debug verification failures
4. Review and ensure that expected Code and functional coverage metrics are achieved

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